With the continuous development of semiconductor technologies, reducing the critical dimension (CD) of the devices of integrated circuits (ICs) has become one of the major approaches to increase the speed of the devices and to enhance the performances of the ICs. Currently, because semiconductor industry has been advanced to the nanoscale technical node during the path for pursuing high device density, high performance and low cost, especially when the sizes of the semiconductor devices reach nanoscale, the fabrication of the semiconductor devices has to face various challenges caused by the limitations of the principles of physics.
When the sizes of the semiconductor devices reach the nanoscale, the critical dimensions of the gate structures (gate CDs) of the semiconductor devices are correspondingly shrunk. With the continuous reduction of the technique node, the conventional gate dielectric layer has become thinner and thinner; and the leakage currents of the transistors are correspondingly increased; and the power waste issues occur in the semiconductor devices. To solve such issues and avoid high temperature processes, an approach that uses a high-K metal gate structure to substitute the polysilicon gate structure has been provided.
During the high-K/metal gate last process, to increase the carrier mobility, stress layers are often formed in the source/drain regions by an epitaxial growth process. For example, a compressive stress material (such as SiGe) is used in the fabrication of a PMOS device; and a tensile stress material (such as SiC) is used in the fabrication of an NMOS device.
However, during the processes for forming the stress layers, it may be easy to deteriorate the performance of the semiconductor devices. The disclosed methods and semiconductor structures are directed to solve one or more problems set forth above and other problems in the art.